CPU Pipelining

A TLDR of this super awesome article: https://substack.com/@bharathw/p-149584645

A CPU executes a set of instructions given to it.

It needs to be able to read an instruction by specifying location and decoding bits, perform any sort of operation, read/write data and handle interrupts.

CPU Performance is determined by Throughput and Latency

Throughput - The number of instructions that are completed per unit time

Latency - The time it takes for 1 instruction from start to end

Different commands take a different amount of time to execute. Waiting for each command to execute sequentially will take forever.

To improve the performance of CPUs we like to run things in parallel to speed things up.

An example to really explain this:

if you have 1 machine to wash and dry your clothes: washing takes 10m and drying takes 20m

if you wanted to do 2 loads it would take you 60m

However, if you had separate machines for washing and drying, you could load the washer when the dryer was going with the 1st load decreasing the time by 10m - 50m

There are 5 stages of pipelining:

• Instruction Fetch

• Operand Fetch and Decode

• Execute

• Memory Access

• Register Write Back

Image from: https://ieeexplore.ieee.org/document/586067

This picture depicts how pipelining works in a cycle!