What is CPU Bitness?
I read this super cool article and here is a TLDR: https://substack.com/@bharathw/p-153459070
When speccing out a CPU, the bitness is one of the factors that come up. The bitness is the number of bits on which a CPU operates in each clock cycle. However, in modern CPUs this definition can vary.
This could be 4 different attributes:
1) Size of the register
2) Size of memory address
3) Size of data bus
4) Instruction size
1) Size of the register
The registers are general purpose storage on the computer where data is stored before arithmetic operations are performed on them. We assume that variables in high-level languages map to one register. The registers inform the size of data the CPU can handle in one clock cycle, the memory address, and the arithmetic operations so more registers can mean better performance since everything else has to increase in size.
2) The size of the memory address
The size of the memory address decides the total number of bits that can be addressed ie an 8 bit memory address can address 256 memory locations (2^8).
If the size of the memory address is larger, means that more memory could have an address -> fewer cache missed and reduced paging. So in general a bigger number is better, however this can be power intensive.
3. Size of the data bus
This is the most confusing since the bus size is not clearly defined. In different systems, data is also read differently making the bus size larger/smaller.
We can assume that data bus size refers to the size of the data bus connecting to the registers, so an increase in size means that more bits are processed in a clock cycle. This could however require more power as well as delays in the chip due to a more complicated routing design.
4. Instruction size
Instruction size refers to the number of bits used to encode an instructions per the ISA being used.
A larger instruction size can be better as more information can be encoded onto it, however it can be disadvantageous as extra space can be filled with unnecessary information. This can cause strain on the pipeline design as more instructions need to be decoded.
The bitness is least likely to be the instruction size since CPUs need to be compatible with older code -> software for a 32 but CPU should work on a 64 bit
